-- File Name:  md.vhd
%A -- Manchester decoder Chip
%A
%A library ieee ;
%A use ieee.std_logic_1164.all ;
%A use ieee.std_logic_arith.all ;
%A
%A entity md is
%A port (rst: in std_logic ;--复位clk1x,no_bits_rcvd,nrz寄存器
%A     clk16x: in std_logic ;--用于时钟，中心采样
%A     mdi: in std_logic ;--串行输入曼码数据
%A     rdn : in std_logic ;--控制信号表示可进行一个读操作
%A dout : out std_logic_vector (7 downto 0) ;
%A data_ready : out std_logic;--状态信号，表示数据已准备好，保持在数据总线上等待输出
%A     nrz2:    out std_logic;
%A     sample2: out std_logic;
%A     nrz3:    out std_logic
%A ) ;
%A end md ;
%A
%A architecture v1 of md is
%A
%A signal clk1x_enable : std_logic ;--使能1x CLOCK接收一个字。高有?
%A signal mdi1 : std_logic ;
%A signal mdi2 : std_logic ;--内部寄存器,用于检测mdi的输入边沿，激活clk1x_enable
%A signal rsr : std_logic_vector (7 downto 0) ;
%A signal dout_i : std_logic_vector (7 downto 0) ;
%A signal no_bits_rcvd : unsigned (3 downto 0) ;--控制字大小(位数),及运行译码频率
%A signal clkdiv : unsigned (3 downto 0) ;
%A signal nrz : std_logic ;
%A signal clk1x : std_logic ;
%A signal sample : std_logic ;--决定接收器对数据进行译码的时刻
%A
%A begin
%A
%A -- Generate two FF register to accept serial Manchester data in
%A
%A process (rst,clk16x)
%A begin
%A if rst = ‘1‘ then
%A mdi1 <= ‘0‘ ;
%A mdi2 <= ‘0‘ ;--
%A elsif clk16x‘event and clk16x = ‘1‘ then
%A mdi2 <= mdi1 ;
%A mdi1 <= mdi ;
%A end if ;
%A end process ;
%A
%A -- Enable the clock when an edge on mdi is detected
%A
%A process (rst,clk16x,mdi1,mdi2,no_bits_rcvd)
%A begin
%A if rst = ‘1‘ then
%A clk1x_enable <= ‘0‘ ;
%A elsif clk16x‘event and clk16x = ‘1‘ then
%A if mdi1 = ‘0‘ and mdi2 = ‘1‘ then
%A clk1x_enable <= ‘1‘ ;
%A else if std_logic_vector(no_bits_rcvd) = "1001" then
%A clk1x_enable <= ‘0‘ ;
%A end if ;
%A end if ;
%A end if ;
%A end process ;
%A
%A -- Center sample the data at 1/4 and 3/4 points in data cell
%A
%A sample <= ((not clkdiv(3)) and (not clkdiv(2)) and clkdiv(1) and clkdiv(0)) or (clkdiv(3) and clkdiv(2) and (not clkdiv(1)) and (not clkdiv(0))) ;
%A sample2<=((not clkdiv(3)) and (not clkdiv(2)) and clkdiv(1) and clkdiv(0)) or (clkdiv(3) and clkdiv(2) and (not clkdiv(1)) and (not clkdiv(0)));
%A --sample;
%A -- Decode Manchester data into NRZ
%A
%A process (rst,sample,mdi2,clk16x,no_bits_rcvd)
%A begin
%A if rst = ‘1‘ then
%A nrz <= ‘0‘ ;
%A elsif clk16x‘event and clk16x = ‘1‘ then
%A if std_logic_vector(no_bits_rcvd) > "000" and sample = ‘1‘ then
%A nrz <= mdi2 xor clk1x ;
%A nrz2<=mdi2 xor clk1x;
%A nrz3<=nrz;
%A end if ;
%A end if ;
%A end process ;
%A
%A -- Increment the clock
%A
%A process (rst,clk16x,clk1x_enable,clkdiv)
%A begin
%A if rst = ‘1‘ then
%A clkdiv <= "0000" ;
%A elsif clk16x‘event and clk16x = ‘1‘ then
%A if clk1x_enable = ‘1‘ then
%A clkdiv <= clkdiv + "0001" ;
%A end if ;
%A end if ;
%A end process ;
%A
%A clk1x <= clkdiv(3) ;
%A
%A -- Serial to parallel conversion
%A
%A process (rst,clk1x,dout_i,nrz)
%A begin
%A if rst = ‘1‘ then
%A rsr <= "00000000" ;
%A elsif clk1x‘event and clk1x = ‘1‘ then
%A rsr <= rsr(6 downto 0) & nrz ;
%A end if ;
%A end process ;
%A
%A -- Transfer from shift to data register
%A
%A process (rst,clk1x,no_bits_rcvd)
%A begin
%A if rst = ‘1‘ then
%A dout_i <= "00000000" ;
%A elsif clk1x‘event and clk1x = ‘1‘ then
%A if std_logic_vector(no_bits_rcvd) = "1001" then
%A dout_i <= rsr ;
%A end if ;
%A end if ;
%A end process ;
%A
%A -- Track no of bits rcvd for word size
%A
%A process (rst,clk1x,clk1x_enable,no_bits_rcvd)
%A begin
%A if rst = ‘1‘ then
%A no_bits_rcvd <= "0000" ;
%A elsif clk1x‘event and clk1x = ‘1‘ then
%A if (clk1x_enable = ‘0‘) then
%A no_bits_rcvd <= "0000" ;
%A else
%A no_bits_rcvd <= no_bits_rcvd + "0001" ;
%A end if ;
%A end if ;
%A end process ;
%A
%A -- Generate data_ready status signal
%A
%A process (rst,clk1x,clk1x_enable,rdn)
%A begin
%A if (rst = ‘1‘ or rdn = ‘0‘) then
%A data_ready <= ‘0‘ ;
%A elsif clk1x‘event and clk1x = ‘1‘ then
%A if (clk1x_enable = ‘0‘) then
%A data_ready <= ‘1‘ ;
%A else data_ready <= ‘0‘ ;
%A end if ;
%A end if ;
%A end process ;
%A
%A dout <= dout_i ;
%A
%A end ;
%A
%A